The present disclosure relates to a counter, a counting method, an AD converter, a solid-state imaging device, and an electronic device, and particularly relates to, for example, a counter, a counting method, an AD converter, a solid-state imaging device, and an electronic device each of which is configured such that the power consumption of a column counter, such as a complementary metal oxide semiconductor (CMOS) image sensor and the like, is reduced.
As a solid-state imaging device used for imaging devices of various electronic devices having an imaging function, a CMOS image sensor (which will be hereinafter referred to as a “CIS”) has been used.
A main trend of the CIS is a column-parallel output type in which each pixel is provided with a floating diffusion (FD) amplifier, pixels arranged in a matrix in a pixel array are sequentially selected in units of rows in a column direction, and the outputs of the floating diffusion amplifiers are read out. This is because, since it is difficult to achieve the sufficient driving capability in the FD amplifier provided in each pixel, the data rate is lowered and parallel processing is considered to be advantageous. Various types of signal output circuits for the column-parallel output type CIS have been proposed.
As a method used for reading pixel signals of the CIS, there is a method in which photocharge output from a photoelectric conversion element such as a photodiode (which will be hereinafter referred to as a “PD”) is temporarily sampled in a capacitor in a later step via a MOS switch arranged in the vicinity of the photodiode and then is read. In this method, however, noises having inverse correlation relative to a sampled capacitance value are generally superposed. Also, in the pixels, when the photocharge is transferred to the capacitor, complete transfer of the photocharge is performed utilizing the potential gradient, and thus, noises are not generated but, when the voltage level of the capacitor is reset to be a predetermined reference value, noises are superposed.
As a typical method used for removing such noises, there is a correlated double sampling (CDS) in which a reset level immediately before sampling of the photocharge is performed is read out and stored, a brightness signal level after the sampling is performed is next read out, and subtraction between these levels is performed, thereby removing the noises.
There are various methods for CDS, and as one of them is a method in which a pixel signal voltage is compared to a Ramp signal voltage by a comparator, AD conversion is performed by counting time until the output of the comparator is inverted, first AD conversion is performed by up count, and second AD conversion is performed by down count, thereby performing CDS in a digital manner (see, for example, Japanese Patent No. 4655500).
FIG. 1 is a block diagram illustrating an example configuration of the CIS including an AD conversion section (which will be hereinafter referred to as an “ADC”) that performs the above-described CDS in a digital manner.
The CIS 10 includes a pixel array section 11, a row scanning section 12, a column scanning section 13, a timing control section 14, an ADC 15 provided for each column, a DAC 16, and a data output section 17.
The pixel array section 11 is configured such that unit pixels 111, each including a photodiode and a pixel amplifier, are arranged in a matrix. The row scanning section 12, the column scanning section 13, and the timing control section 14 are provided to sequentially read out signals of the pixel array section 11. The row scanning section 12 controls a row address and row scanning. The column scanning section 13 controls a column address and column scanning. The timing control section 14 generates an internal clock.
Each of the ADCs 15 is an integral ADC including a comparator (CMP) 151, an asynchronous up and down counter (CNT) 152, and a switch 153.
The comparator 151 compares a ramp waveform RAMP obtained by changing the waveform of a reference voltage generated by the DAC 16 into a step-like form to an analog signal corresponding to photocharge obtained from the corresponding unit pixel 111 via a column line Vn (n=0, 1, . . . , n+1). The asynchronous up and down counter (which will be hereinafter merely referred to as a “counter”) 152 has a function of performing, in response to the output of the comparator 151 and a clock CK, up count (or down count) and holding a result of the count, that is, a count value. The switch 153 connects the counter 152 with a data transfer line 18, and is opened and closed by scanning control from the column scanning section 13. The data output section 17 including a sense circuit corresponding to the data transfer line 18 and a subtraction circuit is provided on the data transfer line 18.
The counter 152 having a function as a holding circuit is initially put into an up count (or down count) state to perform reset count and, when the output CompOut of the corresponding comparator 151 is inverted, the up count operation is stopped and the is held. In this case, the initial value of the counter 152 is an arbitrary value in the gradation of AD conversion, that is, for example, 0. In this reset count period, a reset component ΔV of the unit pixel 111 is read out. Thereafter, the counter 152 is put into a down count (or up count) state to perform data count corresponding to the amount of incident light and, when the output CompOut of the corresponding comparator 151 is inverted, the corresponding to a comparison period is held. The count value held in the counter 152 is received as a digital signal by the data output section 17 via the switch 153 which is closed in accordance with scanning control from the column scanning section 13 and the data transfer line 18.
The column scanning section 13 is activated, for example, by supply of a start pulse STR and a master clock MCK from the timing control section 14 to drive a corresponding selection line SEL in synchronization with a drive clock CLK generated on the basis of the master clock MCK, and causes latch data (the held count value) of the counter 152 to be read out to the data transfer line 18.
In the CIS 10 having the above-described configuration, the following processing is performed within 1 horizontal unit period (1 H).
That is, in the 1 H, assuming that first read out from the unit pixels 111 in a row Hx to the column line Vn (n=0, 1, n+1) is P-phase read out PR, first comparison in the comparator 151 is P-phase comparison PC, second read out is D-phase read out DR, second comparison in the comparator 151 is D-phase comparison DC, and post-processing performed after D-phase processing is post D-phase processing DAP, various operations are continuously performed within 1 H.
Timing control of the P-phase read out PR, the P-phase comparison PC, the D-phase read out DR, the D-phase comparison DC, and the post D-phase processing DAP is performed by the timing control section 14.
Next, a specific function of the counter 152 in the ADC 15 will be described.
The counter 152 has a function of switching, while holding the value, the count mode from up count to down count, or from down count to up count, and a function of performing counting at both edges of rises and falls of an input clock CK, i.e., a function of performing counting at a frequency twice the frequency of the input clock. Also, the counter 152 has a function of subtracting a first count value A from a second count value B to calculate a subtraction value B−A.
In order to achieve the above-described functions, special processing is performed in a least significant bit (LSB) circuit of the counter 152, and therefore, a configuration in which a logic inversion selector is used for an output section of the LSB circuit (see, for example, Japanese Patent No. 4853445) has been employed.
FIG. 2 is a circuit diagram illustrating a first example configuration of the counter 152 using a logic inversion selector for an output of the LSB circuit. FIG. 3 is a diagram illustrating operation waveforms of the CIS 10 when the counter 152 has the first example configuration.
In the first example configuration of the counter 152, the LSB circuit includes a latch circuit 201 that latches the input clock CK, a D type flip-flop circuit (FF) 202 that separately stores the output of the latch circuit 201, and a logic inversion selector 203 that switches between positive and negative inversions of the input clock of the next bit in accordance with data stored in the D type FF 202. The first and subsequent bits in the later stage of the LSB circuit serve as a ripple counter that includes D type FFs 207, 210, and 213 to invert the output of each bit by control from the outside.
FIG. 4 is a circuit diagram illustrating a second example configuration of the counter 152 using a logic inversion selector for an output of the LSB circuit. FIG. 5 is a diagram illustrating operation waveforms of the CIS 10 when the counter 152 has the second example configuration.
In the second example configuration of the counter 152, the LSB circuit includes a latch circuit 201 that latches the input clock CK, a D type FF 202 that separately stores the output of the latch circuit 201, and a logic inversion selector 203 that switches between positive and negative inversions of the input clock of the next bit in accordance with data stored in the D type FF 202. The first and subsequent bits in the later stage of the LSB circuit serve as a ripple counter that includes D type FFs 221 to 223 and logic inversion selectors 224 to 229 that invert the output of each bit by control from the outside.